drivers: timer: nrf_rtc_timer: Allow use of custom bit width #92025
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Out of curiosity, what usecases are there for artificially lowering the counters bit widht? Only effect I can think of is more frequent wakeups to account for rollover, which would be worse for power consumption :) |
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Allowed use of counter bit width lower than hardware 24. In that case, PPI connection is established to trigger clear task once maximum value is reached. Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
Added overlay for the board. Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
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nordic-krch
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Jul 17, 2025
| config NRF_RTC_COUNTER_BIT_WIDTH | ||
| int | ||
| default 15 if SOC_NRF52832 | ||
| default 24 |
| @@ -17,11 +17,21 @@ | |||
| #include <haly/nrfy_rtc.h> | |||
| #include <zephyr/irq.h> | |||
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| /* Ensure that selected counter bit width is within its maximum hardware width. */ | |||
| BUILD_ASSERT(CONFIG_NRF_RTC_COUNTER_BIT_WIDTH <= 24, "Counter bit width exceeds maximum width."); | |||
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Suggested change
| BUILD_ASSERT(CONFIG_NRF_RTC_COUNTER_BIT_WIDTH <= 24, "Counter bit width exceeds maximum width."); | |
| BUILD_ASSERT(CONFIG_NRF_RTC_COUNTER_BIT_WIDTH <= RTC_BIT_WIDTH, "Counter bit width exceeds maximum width."); |
If range is added in Kconfig then it is redundant.
| /* Ensure that selected counter bit width is within its maximum hardware width. */ | ||
| BUILD_ASSERT(CONFIG_NRF_RTC_COUNTER_BIT_WIDTH <= 24, "Counter bit width exceeds maximum width."); | ||
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| #if (CONFIG_NRF_RTC_COUNTER_BIT_WIDTH < 24) |
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Suggested change
| #if (CONFIG_NRF_RTC_COUNTER_BIT_WIDTH < 24) | |
| #if (CONFIG_NRF_RTC_COUNTER_BIT_WIDTH < RTC_BIT_WIDTH) |
| @@ -33,7 +43,7 @@ BUILD_ASSERT(CHAN_COUNT <= CHAN_COUNT_MAX, "Not enough compare channels"); | |||
| BUILD_ASSERT(DT_NODE_HAS_STATUS(DT_NODELABEL(RTC_LABEL), disabled), | |||
| "Counter for RTC1 must be disabled"); | |||
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| #define COUNTER_BIT_WIDTH 24U | |||
| #define COUNTER_BIT_WIDTH CONFIG_NRF_RTC_COUNTER_BIT_WIDTH | |||
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would be good to have
#define RTC_BIT_WIDTH 24
| @@ -560,8 +590,13 @@ void rtc_nrf_isr(const void *arg) | |||
| rtc_pretick_rtc1_isr_hook(); | |||
| } | |||
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| if (nrfy_rtc_int_enable_check(RTC, NRF_RTC_INT_OVERFLOW_MASK) && | |||
| nrfy_rtc_events_process(RTC, NRF_RTC_INT_OVERFLOW_MASK)) { | |||
| if ((nrfy_rtc_int_enable_check(RTC, NRF_RTC_INT_OVERFLOW_MASK) && | |||
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no need to check OVERFLOW event if custom bit width is used.
| @@ -742,7 +781,7 @@ static int sys_clock_driver_init(void) | |||
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| int_mask = BIT_MASK(CHAN_COUNT); | |||
| if (CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT) { | |||
| alloc_mask = BIT_MASK(EXT_CHAN_COUNT) << 1; | |||
| alloc_mask = BIT_MASK(EXT_CHAN_COUNT) << (1 + CUSTOM_COUNTER_BIT_WIDTH); | |||
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With potentially 2 internal channels It would be good to define
#define SYS_CLOCK_CH 0
#define WRAP_CH 1
And use it here and in places where 0 and 1 are used explicitly now.
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Allowed use of counter bit width lower than hardware 24. In that case, PPI connection is established to trigger clear task once maximum value is reached.